VHDLのエラボレート(まとめあげ)時のインスタンス化のエラー

VHDL(テストベンチ)

1library IEEE;2use IEEE.std_logic_1164.all;3use IEEE.std_logic_unsigned.all;4 5entity simple_alu_test is6END simple_alu_test;7 8architecture EX of simple_alu_test is9 constant STEP : Time := 100 ns;10 signal A,B,C,D,SEL1,SEL2 : std_logic;11 component and2 port(12 A, B : in std_logic;13 C : out std_logic );14 end component;15 16 component or2 port(17 A, B : in std_logic;18 C : out std_logic );19 end component;20 21 component xor2 port(22 A, B : in std_logic;23 C : out std_logic );24 end component;25 26 component not1 port(27 A : in std_logic;28 C : out std_logic );29 end component;30 31 component sel4_1 port(32 A,B,C,D : in std_logic;33 SEL1,SEL2 : in std_logic;34 Z : out std_logic );35 end component;36 37 signal o_and2,o_or2,o_xor2,o_not1,o_sel : std_logic;38 39 begin40 U0: and2 port map (A, B, o_and2);41 U1: or2 port map (A, B, o_or2);42 U2: xor2 port map (A, B, o_xor2);43 U3: not1 port map (A, o_not1);44 U4: sel4_1 port map (o_and2,o_or2,o_xor2,o_not1,SEL1,SEL2,o_sel);45 46 process(A,B)47 begin48 o_and2<=A and B;49 o_or2<=A or B;50 o_xor2<=A xor B;51 o_not1<= not A;52 end process;53 54 process(SEL1,SEL2)55 begin56 if (SEL1='0' and SEL2='0')then57 o_sel <= o_and2;58 elsif (SEL1='0' and SEL2='1')then59 o_sel <= o_or2;60 elsif (SEL1='1' and SEL2='0')then61 o_sel <= o_xor2;62 else63 o_sel <= o_not1;64 end if;65 end process;66 end EX;