Vivadoによるカウンタ作成

実現したいこと

• btn0をおすとカウンタのスタートとストップができる
• sw0が0のときはカウントアップ、sw1が1のときはカウントダウン
• sw1が0のときは16進、sw1が1のときは10進のカウンタ

前提

発生している問題・エラーメッセージ

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 8 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btn0, and sw1.

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 8 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btn0, and sw1.

該当のソースコード

HDL（.vファイル）

1`timescale 1ns / 1ps 2////////////////////////////////////////////////////////////////////////////////// 3// Company: 4// Engineer: 5// 6// Create Date: 2023/07/18 14:02:29 7// Design Name: 8// Module Name: task22_x_202211666 9// Project Name: 10// Target Devices: 11// Tool Versions: 12// Description: 13// 14// Dependencies: 15// 16// Revision: 17// Revision 0.01 - File Created 18// Additional Comments: 19// 20////////////////////////////////////////////////////////////////////////////////// 21 22 23module task22_x_202211666( 24 input clk, 25 input btn0, 26 input sw0, //0でカウントアップ 27 input sw1, //1で10進 28 output [3:0]ld 29 ); 30 31reg [3:0]hexcnt; 32reg [31:0]scnt; 33reg r0,r1; 34wire pulse; 35always@(posedge clk)begin 36 r0 <= btn0; 37 r1 <= r0; 38end 39 40 41parameter SMAX = 125000000-1; 42 43initial begin 44 hexcnt <= 0; 45 scnt <= 0; 46end 47assign pulse = r1 & ~r0; 48 49reg en; 50always@(posedge clk)begin 51 if(pulse == 1)begin 52 en <= ~en; 53 end 54end 55 56 57always@(posedge clk)begin 58 if(scnt < SMAX)begin 59 scnt <= scnt + 1; 60 end else begin 61 scnt <= 0; 62 end 63end 64 65always@(posedge clk) 66 if(scnt == SMAX)begin 67 if(en == 1)begin 68 if(sw1 == 1)begin //10進 69 if(sw0 == 0)begin //up 70 if(hexcnt == 9)begin 71 hexcnt <= 0; 72 end else begin 73 hexcnt <= hexcnt + 1; 74 end 75 end else begin 76 hexcnt <= hexcnt - 1; 77 end 78 end else begin //16進 79 if(sw0 == 0)begin //up 80 hexcnt <= hexcnt + 1; 81 end else begin 82 hexcnt <= hexcnt - 1; 83 end 84 end 85 end 86 end 87 88assign ld = hexcnt; 89 90endmodule 91

HDL（.xdcファイル）

1set property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {clk}]; 2create_clock -period 8.000 -name sys_clk_pin -waveform {0 4} -add [get_ports {clk}]; 3 4set property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {ld[0]}]; 5set property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {ld[1]}]; 6set property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {ld[2]}]; 7set property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {ld[3]}]; 8 9set property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {btn0}]; 10 11set property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {sw0}]; 12set property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {sw1}]; 13

試したこと

xdcファイルに原因がありそうなので、タイプミスを確認したがタイプミスはなかった。chatGPTにもかけてみたが、正しそうだった。

補足情報（FW/ツールのバージョンなど）

vivado 2023.1
windows11