実現したいこと
VHDLにて、A,B,Cを入力、Xを出力として、
論理式X = /A*/BC+/AB*/C+A*/BC+AB*C
で表される論理回路を記述し、テストベンチで検証をしたいです。
発生している問題・分からないこと
しかし文法への理解が甘いためか、宣言がされていないというエラーが出てしまいます。どなたかご教授いただけると幸いです。
エラーメッセージ
error
1--重要と考えられるエラーメッセージ 2ERROR: [VRFC 10-2989] 'a' is not declared [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:49] 3ERROR: [VRFC 10-2989] 'b' is not declared [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:50] 4ERROR: [VRFC 10-2989] 'c' is not declared [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:51] 5 6--実行後のコンソール全文 7Command: launch_simulation 8INFO: [Vivado 12-12493] Simulation top is 'tb_report_check' 9WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set) 10INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/free/vivado_project/HW2/HW2.sim/sim_1/behav/xsim' 11INFO: [SIM-utils-51] Simulation object is 'sim_1' 12INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2023.2/tps/boost_1_72_0' 13INFO: [SIM-utils-54] Inspecting design source files for 'tb_report_check' in fileset 'sim_1'... 14INFO: [USF-XSim-97] Finding global include files... 15INFO: [USF-XSim-98] Fetching design files from 'sim_1'... 16INFO: [USF-XSim-2] XSim::Compile design 17INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/free/vivado_project/HW2/HW2.sim/sim_1/behav/xsim' 18"xvhdl --incr --relax -prj tb_report_check_vhdl.prj" 19ECHO は <OFF> です。 20ECHO は <OFF> です。 21INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/free/vivado_project/HW2/src/design_src2.vhd" into library xil_defaultlib 22INFO: [VRFC 10-3107] analyzing entity 'report_check' 23INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/free/vivado_project/HW2/src/tb_src2.vhd" into library xil_defaultlib 24INFO: [VRFC 10-3107] analyzing entity 'tb_report_check' 25ERROR: [VRFC 10-2989] 'a' is not declared [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:49] 26ERROR: [VRFC 10-2989] 'b' is not declared [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:50] 27ERROR: [VRFC 10-2989] 'c' is not declared [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:51] 28ERROR: [VRFC 10-4982] syntax error near '=>' [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:52] 29ERROR: [VRFC 10-1471] type error near x_tb ; current type std_logic; expected type void [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:52] 30ERROR: [VRFC 10-9458] unit 'sim' is ignored due to previous errors [C:/Users/free/vivado_project/HW2/src/tb_src2.vhd:9] 31INFO: [VRFC 10-8704] VHDL file 'C:/Users/free/vivado_project/HW2/src/tb_src2.vhd' is ignored due to errors 32INFO: [USF-XSim-69] 'compile' step finished in '2' seconds 33INFO: [USF-XSim-99] Step results log file:'C:/Users/free/vivado_project/HW2/HW2.sim/sim_1/behav/xsim/xvhdl.log' 34ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/free/vivado_project/HW2/HW2.sim/sim_1/behav/xsim/xvhdl.log' file for more information. 35ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. 36ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. 37WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:\Users\free\vivado_project\HW2\src\tb_src2.vhd:] 38WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [C:\Users\free\vivado_project\HW2\src\design_src2.vhd:]
該当のソースコード
VHDL
1--デザインソース2library IEEE;3use IEEE.STD_LOGIC_1164.ALL;4entity report_check is5 Port ( A : in STD_LOGIC;6 B : in STD_LOGIC;7 C : in STD_LOGIC;8 X : out STD_LOGIC);9end report_check;10 11architecture Behavioral of report_check is12signal s1: std_logic;13signal s2: std_logic;14signal s3: std_logic;15signal s4: std_logic;16begin17 process(A,B,C)18 begin19 s1 <= (not A) and (not B) and C;20 s2 <= (not A) and B and (not C);21 s3 <= A and (not B) and C;22 s4 <= A and B and C;23 X <= s1 or s2 or s3 or s4;24 end process;25end Behavioral;26 27
VHDL
1--テストベンチ：(A,B,C)の0,1を変化させた全８パターンを１秒ごとに入力2library IEEE;3 use IEEE.STD_LOGIC_1164.ALL;4 use IEEE.STD_LOGIC_ARITH.ALL;5 use IEEE.STD_LOGIC_UNSIGNED.ALL;6 7 entity tb_report_check is8 end tb_report_check;9 10 architecture SIM of tb_report_check is11 component report_check 12 port(13 A : in STD_LOGIC;14 B : in STD_LOGIC;15 C : in STD_LOGIC;16 X : out STD_LOGIC);17 end component;18 signal A_tb : STD_LOGIC := '0';19 signal B_tb : STD_LOGIC := '0';20 signal C_tb : STD_LOGIC := '0';21 signal X_tb : STD_LOGIC;22 constant period : time := 1 sec; 23 begin24 target_instance: entity work.report_check port map (25 A <= A_tb 26 ,B <= B_tb 27 ,C <= C_tb 28 ,X => X_tb 29 );30 process begin31 A_tb <= '1';32 wait for period;33 B_tb <= '1';34 wait for period;35 A_tb <= '0';36 wait for period;37 B_tb <= '0';38 wait for period;39 C_tb <= '1';40 wait for period;41 A_tb <= '1';42 wait for period;43 B_tb <= '1';44 wait for period;45 A_tb <= '0';46 wait for period;47 end process;48 49 process(A_tb, B_tb, C_tb) begin50 A <= A_tb;51 B <= B_tb;52 C <= C_tb;53 X => X_tb;54 end process;55 end SIM;
試したこと・調べたこと
上記の詳細・結果
VivadoにてRun simulationを行うと、インスタンスtarget_instanceを作成する部分で最初のエラー箇所が見られ、'a' is not declared(b,cも同様)と出ます。
補足
特になし
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